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FPU
CHAPTER 7
Background information
Register
Width [bits]
Explanation
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FPCR
FPSR
FPIAR
64
64
64
64
64
64
64
64
32
32
32
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
data register 0
data register 1
data register 2
data register 3
data register 4
data register 5
data register 6
data register 7
control register
status register
instruction address register
Table 7.3: FPU registers
MAC/EMAC
Register
MACSR
ACC0
ACC1
ACC2
ACC3
ACCext01
ACCext23
MASK
Width [bits]
32
32
32
32
32
32
32
32
Explanation
MAC status register
MAC accumulator 0
MAC accumulator 1 (EMAC only)
MAC accumulator 2 (EMAC only)
MAC accumulator 3 (EMAC only)
ACC0 and ACC1 extensions
ACC2 and ACC3 extensions
MAC mask register
Table 7.4: MAC/EMAC registers
Supervisor
All supervisor registers are only accessible when the CPU is in supervisor mode.
Register
SR
OTHER_A7
VBR
CACR
ASID
ACR0
ACR1
ACR2
ACR3
MMUBAR
Width [bits]
16
32
32
32
32
32
32
32
32
32
Explanation
Status register (the lower 8-bits are the CCR)
Supervisor A7 stack pointer
Vector base register
Cache control register
Address space ID register
Access control register 0 (data)
Access control register 1 (data)
Access control register 2 (instruction)
Access control register 3 (instruction)
MMU base address register
Table 7.5: Supervisor registers
J-Link ColdFire BDM 26 (UM08009)
? 2004-2009 SEGGER Microcontroller GmbH & Co. KG
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